1. Field of the Invention
This invention relates to packages to encapsulate one or more integrated circuit devices, and more particularly to a method for the manufacture of a no external lead package having a die pad and at least one of a power ring or ground ring circumscribing the die pad.
2. Description of the Related Art
In lead frame based semiconductor packages, electrical signals are transmitted between at least one integrated circuit device (die) and external circuitry, such as a printed circuit board, by an electrically conductive lead frame. The lead frame includes a number of leads, each having an inner lead end and an opposing outer lead frame end. The inner lead ends are electrically interconnected to input/output (I/O) pads on the die and the outer lead ends provide terminals outside the package body for interconnection to external circuitry. When the outer lead end terminates at a sidewall of the package body, the package is known as a “no lead” package. If the outer leads extend beyond the package body perimeter, the package is referred to as “leaded.” Examples of well known no-lead packages include quad flat no lead (QFN) packages which have four sets of leads disposed around the perimeter of the bottom of a square package body and dual flat no lead (DFN) packages which have two sets of lead disposed along opposite sides of the bottom of a package body.
Interconnection of the die to the inner lead ends is typically performed using wire bonding, tape automated bonding (TAB) or flip chip bonding. In wire bonding or TAB bonding, the inner lead ends terminate a distance from the die and are electrically interconnected to I/O pads on an electrically active face of the die by small diameter wires or conductive tape. The die may be supported by a die pad which is surrounded by the leads. In flip chip bonding, the inner lead ends of the lead frame extend beneath the die and the die is flipped so that the I/O pads on the electrically active face of the die contact the inner lead ends by a direct electrical contact, such as a solder joint.
A representative QFN package and its method of manufacture is more fully disclosed in commonly owned U.S. patent application Ser. No. 10/563,712 published as PCT International Application No. WO2005/017968 A2 on Feb. 24, 2005. The disclosure of U.S. patent application Ser. No. 10/563,712 is incorporated by reference in its entirety herein.
In certain package configurations, multiple I/O pads and the circuitry on the electrically active face of the integrated circuit device associated with those I/O pads are to be at a common voltage or interconnected to a common ground. Rather than interconnecting these I/O pads to multiple leads, it is known in a dielectric substrate type package to form one or more conductive rings around the die pad and utilize these rings as common voltage buses or common ground. FIG. 1 of U.S. Pat. No. 6,812,580 to Wenzel et al. discloses two ring-shaped power buses. However, it has not been known to form such power buses in a lead-frame based package, such as a QFN. For example, FIG. 6 of U.S. Pat. No. 6,812,580 shows the die pad as a ground and a lead as a signal source. U.S. Pat. No. 6,812,580 is incorporated by reference in its entirety herein.
Lead frame based packages have better thermal performance, that is they conduct heat away from the integrated circuit device more efficiently, than substrate based packages. A lead frame based package having at least one power and/or ground bus circumscribing a die pad would have improved thermal and electrical properties over presently available no-lead packages. There remains, a need for such a package in the art.